Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, it relates to a semiconductor memory device capable of preventing soft errors caused by radioactive rays such as alpha rays.
Description of the Prior Art
Conventionally, a dynamic RAM (Random Access Memory) which stores data depending on presence or absence of stored charges has been known as a semiconductor memory device.
FIG. 1 is a cross sectional view showing a structure of a peripheral portion of a memory cell in a 256 k dynamic RAM as an example of such a conventional semiconductor memory.
Description is now made of the structure of the peripheral portion of the memory cell shown in FIG. 1.
In FIG. 1, a p.sup.+ -type region 10 for preventing inversion and parasitism is formed on a p.sup.- -type semiconductor substrate 1, and an insulator film 9 for isolating elements is formed on the p.sup.+ -type region 10. In addition, an n.sup.+ -type region 6 and an n.sup.+ -type region 7 are formed spaced apart from each other on the p.sup.- -type semiconductor substrate 1, and a p.sup.+ -type region 8 is formed on the p.sup.- -type semiconductor substrate 1 between the n.sup.+ -type region 6 and the n.sup.+ -type region 7. Furthermore, a first gate insulator film 4 is formed on a part of the n.sup.+ -type region 6 and the insulator film 9. A first gate electrode 2 connected to a power supply (not shown) through a terminal 13 is formed on the first gate insulator film 4. Additionally, a second gate insulator film 5 is formed on the p.sup.+ -type region 8, an end of the n.sup.+ -type region 6, and an end of the n.sup.+ -type region 7. A second gate electrode 3 connected to a word line (not shown) through a terminal 14 is formed on the second gate insulator film 5. The right portion located under the first gate insulator film 4, within the n.sup.+ -type region 6 serves as a charge storage region for storing data, while the remaining left portion serves as one source/drain region of a transfer gate transistor. The charge storage region, the first gate insulator film 4 and the first gate electrode 2 constitute a memory cell. The n.sup.+ -type region 7 is connected to a bit line (not shown) and serves as the other source/drain region of the transfer gate transistor. The p.sup.+ -type region 8 serves to control the threshold voltage of the second gate electrode 3. Thus, the transfer gate transistor comprises the p.sup.- -type semiconductor substrate 1, the n.sup.+ -type region 6, the n.sup.+ -type region 7, the p.sup.+ -type region 8, the second gate insulator film 5 and the second gate electrode 3. A depletion layer 11 is formed between the n.sup.+ -type region 6 and the p.sup.- -type semiconductor substrate 1, and a depletion layer 12 is formed between the n.sup.+ -type region 7 and the p.sup.- -type semiconductor substrate 1.
For simplicity of illustration, an interlayer insulation film formed on the exposed portion in the n.sup.+ -type region 6, the second gate electrode 3 and the n.sup.+ -type region 7, interconnection portions such as a bit line formed on the interlayer insulation film, and a protective layer formed on the interlayer insulation film and the interconnection portions are omitted in FIG. 1. Instead of forming the n.sup.+ -type region 6 serving as an impurity diffusion region, a positive potential may be applied to the first gate electrode 2 to induce an n.sup.+ -type inversion layer on a portion corresponding to the n.sup.+ -type region 6 on the p.sup.- -type semiconductor substrate 1 through the first gate insulator film 4, thereby to store charges therein.
Description is now made on the operation of the peripheral portion of the memory cell shown in FIG. 1.
In the semiconductor memory device shown in FIG. 1, a state in which electrons are stored in the n.sup.+ -type region 6 serving as a charge storage region in the memory cell is defined as "0" and a state in which electrons are not stored therein is defined as "1". The potential of the n.sup.+ -type region 7 connected to a bit line (not shown) is held at a predetermined intermediate level by a sense amplifier (not shown).
When the potential of a word line is increased and the potential of the second gate electrode 3 in the transfer gate transistor connected to the word line exceeds the threshold voltage, a channel of an n.sup.+ -type inversion layer is formed directly under the second gate electrode 3, so that the channel is rendered conductive between the n.sup.+ -type region 6 and the n.sup.+ -type region 7.
When storage data of the memory cell is "0", that is, when electrons are stored in the n.sup.+ -type region 6, the potential of the n.sup.+ -type region 7, which has been so far held at an intermediate level, is decreased by conduction between the n.sup.+ -type region 6 and the n.sup.+ -type region 7 connected to the bit line. On the other hand, if and when storage data of the memory cell is "1", that is, when electrons are not stored in the n.sup.+ -type region 6, the potential of the n.sup.+ -type region 7, which has been at an intermediate level, is increased by that conduction. Such potential change of the bit line is sensed by the sense amplifier so that the same is amplified and extracted, while the same storage data is refreshed to be rewritten in the memory cell within the same cycle.
The peripheral portion of the conventional memory cell shown in FIG. 1 is operated as described above. However, since the source/drain region and the charge storage region are formed of an n.sup.+ -type region or an n.sup.+ -type inversion layer, electrons out of electron-hole pairs generated upon incidence of radioactive rays such as alpha rays into a memory chip are collected in the n.sup.+ -type region 6 and the n.sup.+ -type region 7, so that there occurs malfunctions (referred to as soft errors hereinafter) in which original storage data are inverted.
A method for preventing soft errors induced by such alpha rays is disclosed in, for example, an article by George A. Sai-Halasz et al., entitled "Alpha-Particle-Induced Soft Error Rate in VLSI Circuits", IEEE TRANSACTIONS ON ELECTRON DEVICES, Vol. ED-29, No. 4, April, 1982, pp. 725-731.
FIG. 2 shows an example of a conventional semiconductor memory device for preventing occurrence of soft errors as described above. More specifically, in FIG. 2, a p.sup.+ -type region 15 is formed around the n.sup.+ -type region 6 to increase memory cell capacity, that is, critical charge capacity so that malfunctions may not be caused even if electrons generated by radioactive rays such as alpha rays are collected in the n.sup.+ -type region 6, whereby occurrence of soft errors can be prevented.
However, the n.sup.+ -type region 7 connected to a bit line is not protected from collection of electrons and even if a p.sup.+ -type region is provided additionally around the n.sup.+ -type region 7, p.sup.+ -type regions are arranged opposed to each other within a narrow spacing of at most 2 to 3 .mu.m to cause operation of a parasitic pnp transistor, so that it becomes difficult to operate the transfer gate transistor stably.
In addition, a semiconductor memory device having a fine structure shown in FIGS. 1 and 2 presents a problem of increase of interconnection resistance of a gate electrode or the like.